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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. 00d 02/15/06 issi ? is43r32400a copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? clock frequency: 200, 166, 100 mhz ? power supply (v dd and v ddq ): 2.5v ? sstl 2 interface ? four internal banks to hide row pre-charge and active operations ? commands and addresses register on positive clock edges (clk) ? bi-directional data strobe signal for data cap- ture ? differential clock inputs (clk and clk ) for two data accesses per clock cycle ? data mask feature for writes supported ? dll aligns data i/o and data strobe transitions with clock inputs ? half-strength and matched drive strength options ? programmable burst length for read and write operations ? programmable cas latency (3, 4, 5 clocks) ? programmable burst sequence: sequential or interleaved ? burst concatenation and truncation supported for maximum data throughput ? auto pre-charge option for each read or write burst ? 4096 refresh cycles every 32ms ? auto refresh and self refresh modes ? pre-charge power down and active power down modes ? industrial temperature availability ? lead-free availability 4meg x 32 128-mbit ddr sdram preliminary information february 2006 is43r32400a 1m x32x4 banks v dd : 2.5v v ddq : 2.5v 144-ball bga device overview i ssi?s 128-mbit ddr sdram achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. the 134,217,728-bit memory array is internally organized as four banks of 32m-bit to allow concurrent operations. the pipeline allows read and write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. the programmable features of burst length, burst sequence and cas latency enable further advantages. the device is available in 32-bit data word size. input data is registered on the i/o pins on both edges of data strobe signal(s), while output data is referenced to both edges of data strobe and both edges of clk. commands are registered on the positive edges of clk. auto refresh, active power down, and pre-charge power down modes are enabled by using clock enable (cke) and other inputs in an industry-standard sequence. all input and output voltage levels are compatible with sstl 2. key timing parameters parameter -5 -6 unit clk cycle time (min.) cas latency = 5 56 ns cas latency = 4 56 ns cas latency = 3 56 ns clk frequency (max.) cas latency = 5 200 166 mhz cas latency = 4 200 166 mhz cas latency = 3 200 166 mhz
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a clk clk cke cs ras cas we a 9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a11 command decoder & clock generator mode register refresh controller refresh counter self refresh controller row address latch multiplexer column address latch burst counter column address buffer column decoder data in buffer data out buffer i/o 0-31 v dd /v ddq v ss /v ss q 14 14 12 8 12 12 2 12 8 32 32 32 32 256 (x 32) 40 9 6 40 9 6 40 9 6 row decoder 40 9 6 memory cell array bank 0 sense amp i/o gate bank control logic row address buffer a10 4 dm0-dm3 dqs0-dqs3 4 functional block diagram ( x 32)
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. 00d 02/15/06 issi ? is43r32400a a b c d e f g h j k l m dqs0 dq4 dq6 dq7 dq17 dq1 9 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc vssq nc vssq vdd vddq vddq nc vddq vddq vdd nc ba0 dq3 vddq vssq vss vssq vssq vssq vssq vssq vss ba1 a0 dq2 dq1 vssq vssq vss vss vss vss vss a10 a2 a1 dq0 vddq vdd vss vss vss vss vss vss vdd a11 a3 dq31 vddq vdd vss vss vss vss vss vss vdd a 9 a4 dq2 9 dq30 vssq vssq vss vss vss vss vss nc a5 a6 dq28 vddq vssq vss vssq vssq vssq vssq vssq vss nc a7 vssq nc vssq vdd vddq vddq nc vddq vddq vdd ck a8 dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq 9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc nc vref 1 2 3 4 5 6 7 8 9 10 11 12 pin configuration package code: b 144-ball fbga (top view) (12.00 mm x 12.00 mm body, 0.8 mm ball pitch) note: vss balls inside the dotted box are optional for purposes of thermal dissipation.
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a pin functions symbol type function (in detail) a0-a11 input pin address inputs are sampled during several commands. during an active command, a0-a11 select a row to open. during a read or write command, a0-a7 select a starting column for a burst. during a pre-charge command, a8 determines whether all banks are to be pre-charged, or a single bank. during a load mode register command, the address inputs select an operating mode. ba0, ba1 input pin bank address inputs are used to select a bank during active, pre-charge, read, or write commands. during a load mode register command, ba0 and ba1 are used to select between the base or extended mode register cas input pin cas is column access strobe, which is an input to the device command along with ras and we . see ?command truth table? for details. cke input pin clock enable: cke high activates and cke low de-activates internal clock signals and input/output buffers. when cke goes low, it can allow self refresh, pre-charge power down, and active power down. cke must be high during entire read and write accesses. input buffers except clk, clk , and cke are disabled during power down. cke uses an sstl 2 input, but will detect a lvcmos low level after vdd is applied. clk, clk input pin all address and command inputs are sampled on the rising edge of the clock input clk and the falling edge of the differential clock input clk . output data is referenced from the crossings of clk and clk . cs input pin the chip select input enables the command decoding block of the device. when cs is disabled, a nop occurs. see ?command truth table? for details. multiple ddr sdram devices can be managed with cs . dm0-dm3 input pin these are the data mask inputs. during a write operation, the data mask input allows masking of the data bus. dm is sampled on each edge of dqs. there are four data mask input pins for the x32 ddr sdram. each input applies to dq0-dq7, dq8-dq15, dq16-dq23, or dq24-dq31. dqs0-dqs3 input/output pin these are the data strobe inputs. the data strobe is used for data capture. during a read operation, the dqs output signal from the device is edge- aligned with valid data on the data bus. during a write operation, the dqs input should be issued to the ddr sdram device when the input values on dq inputs are stable. there are four data strobe pins for the x32 ddr sdram. each of the four data strobe pins applies to dq0-dq7, dq8- dq15, dq16-dq23, or dq24-dq31. dq0-dq31 input/output pin the pins dq0 to dq31 represent the data bus. for write operations, the data bus is sampled on data strobe. for read operations, the data bus is sampled on the crossings of ck and ck . nc ? no connect: this pin should be left floating. these pins could be used for 256mbit or higher density ddr sdram. ras input pin ras is row access strobe, which is an input to the device command along with cas and we . see ?command truth table? for details. we input pin we is write enable, which is an input to the device command along with ras and cas . see ?command truth table? for details. vddq power supply pin vddq is the output buffer power supply. vdd power supply pin vdd is the device power supply. vref power supply pin vref is the reference voltage for sstl 2. vssq power supply pin vssq is the output buffer ground. vss power supply pin vss is the device ground.
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. 00d 02/15/06 issi ? is43r32400a command truth table function cke (n - 1) cke (n) cs cs cs cs cs ras cas cas cas cas cas we we we we we ba1 ba0 address device deselect (nop) h x h xxxxx x no operation (nop) h x l h h h x x x burst stop (2) hhlhhlxxx read (3) h x lhlhvv v write (3) hxlhllvvv bank and row activate h x l l h h v v v pre-charge select bank h x l l h l v v x pre-charge all banks h x l l h l x x x load mode register (base) h x llllll v load extended mode register h x lllllh v auto refresh h x l l l h x x x self refresh l x l l l h x x x notes: 1. h = vih, l = vil, x = vih or vil, v = valid data. 2. this command only applies to read command with auto pre-charge disabled. 3. auto pre-charge is enabled with a8 = h (x32). data mask truth table function cke (n - 1) cke (n) dm0 dm1 dm2 dm3 write enable for data byte dq 0 -dq 7 h xlxxx write disable for data byte dq 0 -dq 7 h xhxxx write enable for data byte dq 8 -dq 15 hxxlxx write disable for data byte dq 8 -dq 15 hxxhxx write enable for data byte dq 16 -dq 23 h xxxlx write disable for data byte dq 16 -dq 23 h xxxhx write enable for data byte dq 24 -dq 31 h xxxxl write disable for data byte dq 24 -dq 31 h xxxxh notes: 1. h = vih, l = vil, x = vih or vil, v = valid data.
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a detailed command truth table - same banks function (n) command (n) prior state (n - 1) cke (n - 1) cke (n) cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we nop or continue deselect any h h h x x x previous operation nop or continue nop any h h l h h h previous operation activate row active idle h h l l h h issue auto refresh auto refresh idle h h l l l h load the base/ load mode register idle h h l l l l extended mode register start read burst read row active h h l h l h read read underway h h l h l h read write underway h h l h l h start write burst write row active h h l h l l write (1) read underway h h l h l l write write underway h h l h l l de-activate row, pre-charge row active h h l l h l start pre-charge truncate read burst, pre-charge read underway h h l l h l start pre-charge truncate write burst, pre-charge write underway h h l l h l start pre-charge terminate read burst burst terminate read underway h h l h h l note: 1. a write command may be terminated only at the completion of the read burst. however, a burst terminate can be transmitted to end the read burst early so that a write command can be asserted.
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. 00d 02/15/06 issi ? is43r32400a detailed command truth table - different banks (bank b, then bank g) function (n) command (n) prior state (n - 1) cke (n - 1) cke (n) cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we nop or continue deselect any h h h x x x previous operation nop or continue nop any h h l h h h previous operation issue any command to any command idle h h x x x x bank g otherwise valid start read burst in read row in bank b h h l h l h bank g active, activating, or pre-charging read read underway in h h l h l h bank b (auto pre- charge disabled) read write underway in h h l h l h bank b (auto pre- charge disabled) read read underway in h h l h l h bank b (auto pre- charge enabled) read write underway in h h l h l h bank b (auto pre- charge enabled) start write burst in bank g write row in bank b active, h h l h l l activating, or pre-charging write (1) read underway in h h l h l l bank b (auto pre- charge disabled) write write underway in h h l h l l bank b (auto pre- charge disabled) write (1) read underway in h h l h l l bank b (auto pre- charge enabled) write write underway in h h l h l l bank b (auto pre- charge enabled)
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a detailed command truth table - low power modes function (n) command (n) prior state (n - 1) cke (n - 1) cke (n) cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we maintain power down don?t care power down mode l l x x x x maintain self refresh don?t care self refresh mode l l x x x x exit power down deselect or nop power down l h x x x x exit self refresh mode deselect or nop self refresh mode l h x x x x enter pre-charge deselect or nop all banks idle h l x x x x power down mode enter active power deselect or nop bank(s) active h l x x x x down mode enter self refresh auto refresh all banks idle h l l l l h mode detailed command truth table - different banks (bank b, then bank g) -cont. function (n) command (n) prior state (n - 1) cke (n - 1) cke (n) cs cs cs cs cs ras ras ras ras ras cas cas cas cas cas we we we we we start pre-charge pre-charge row in bank b active, h h l l h l activating, or pre-charging pre-charge read underway in h h l l h l bank b (auto pre- charge disabled) pre-charge write underway in h h l l h l bank b (auto pre- charge disabled) pre-charge read underway in h h l l h l bank b (auto pre- charge enabled) pre-charge write underway in h h l l h l bank b (auto pre- charge enabled) note: 1. a write command may be terminated only at the completion of the read burst. however, a burst terminate can be transmitted to end the read burst early so that a write command can be asserted.
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. 00d 02/15/06 issi ? is43r32400a absolute maximum ratings (1) symbol parameters rating unit v dd max maximum supply voltage ?0.3 to +3.6 v v ddq max maximum supply voltage for output buffer 0.3 to +3.6 v v in , v ref input voltage, reference voltage ?0.3 to v ddq + 0.3 v v out output voltage ?0.3 to v ddq + 0.3 v p d max allowable power dissipation 2 w i cs output shorted current 50 ma t opr operating temperature com. 0 to +70 c ind. ?40 to +85 t stg storage temperature ?55 to +150 c capacitance characteristics (at t a = 0 to +25c, v dd = v ddq = 2.5v, f = 1 mhz) symbol parameter mi n. max. unit c in1 input capacitance: address, b0, b1 4 5 pf c in2 input capacitance:all other input pins 3 5 pf c in 3 data mask input/output capacitance: dm0 - dm3 6 8 pf c out data input/output capacitance: dq and dqs 6 8 pf notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all voltages are referenced to vss. recommended dc operating conditions (sstl_2 input/output, t a = 0 o c to +70 o c) symbol parameter test condition min typ. max unit v dd supply voltage 2.375 2.500 2.625 v v ddq i/o supply voltage 2.375 2.500 2.625 v v tt i/o termination voltage v ref - 0.04 v ref v ref + 0.04 v v ih input high voltage v ref + 0.15 ? v ddq + 0.3 v v il input low voltage v ssq - 0.3 ? v ddq - 0.15 v v ref i/o reference voltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v i il input leakage current 0 v ref v dd , with all inputs -5 ? 5 a at v ss , except tested input i ol output leakage current output disabled; -5 ? 5 a 0v v out v ddq v oh output high voltage i oh = -15.2ma v tt + 0.76 ? ? v level v ol output low voltage i ol = +15.2ma ? ? v ref - 0.76 v level note: 1. v ddq must always be less than or equal to v dd .
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a dc electrical characteristics (v dd = 2.5v +/- 5%, t a = 0 o c to +70 o c) symbolparameter test condition unit i dd 0 operating current one bank operation; active-precharge; dq, dm and dqs inputs change once per clock cycle; address and control inputs change once per two clock cycles; trc = trc (min); tck = tck (min) 160 ma i dd 1 operating current one bank operation; active-read-precharge; bl = 4; cl = 4; address and control inputs change once per clock cycle; trcdrd = 4 x tck; trc = trc (min); tck = tck (min); iout = 0ma; 240 ma i dd 2 p precharge power-down all banks idle; tck = tck (min); cke = low 40 ma standby current i dd 2 n idle standby current all banks idle; address and control inputs change once per clock cycle; cke = high; cs = high (deselect); vin = vref for dq, dqs, and dm; tck = tck (min) 80 ma i dd 3 p active power-down one bank active; cke = low; tck = tck (min) 40 ma standby current i dd 3 n active standby current one bank active; cs = high; cke = high; address and control inputs change once per clock cycle; dq, dqs, and dm change twice per clock cycle; trc = trc (max); tck = tck (min) 100 ma i dd 4 r operating current one bank active; bl = 2; address and control inputs burst read change once per clock cycle; tck = tck (min); iout = 0ma 420 ma i dd 4 w operating current one bank active; bl = 2; address and control inputs change burst write once per clock cycle; dq, dqs, dm change twice per clock cycle; tck = tck (min) 270 ma i dd 5 auto refresh current trc = trfc (min); tck = tck (min) 280 ma i dd 6 self refresh current cke 0.2v; tck = tck (min) 3 ma i dd 7 operating current four bank interleaved reads with auto precharge; bl = 4; address and controls inputs change per read, write, or active command; trc = trc (min); tck = tck (min) 550 ma notes: 1.operating outside the ?absolute maximum ratings? may lead to temporary or permanent device failure. 2.power up sequence describe in ?initialization? section. 3. all voltages are referenced to v ss .
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. 00d 02/15/06 issi ? is43r32400a ac electrical characteristics (v dd = 2.5v +/- 5%, t a = 0 o c to +70 o c) -5 -6 symbol parameter t est condition min. max. min. max. unit t ck clock cycle time cl = 3 5 10 6 10 ns cl = 4 5 10 6 10 ns cl = 5 5 10 6 10 ns t ch clock high level width 0.45 0.55 0.45 0.55 t ck t cl clock low level width 0.45 0.55 0.45 0.55 t ck t dqsck dqs-out access time from clk, clk -0.7 0.7 -0.7 0.7 ns t ac output access time from clk, clk -0.85 0.85 -0.85 0.85 ns t dqsq dqs-dq skew ? 0.45 ? 0.45 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.4 0.6 0.4 0.6 t ck t dqss clk to valid dqs-in 0.85 1.15 0.85 1.15 t ck t wpres dqs-in setup time 0 ? 0 ? ns t wpreh dqs-in hold time 0.35 ? 0.35 ? ns t wpst dqs write post postamble 0.4 0.6 0.4 0.6 t ck t dqsh dqs-in high level pulse width 0.4 0.6 0.4 0.6 t ck t dqsl dqs-in low level pulse width 0.4 0.6 0.4 0.6 t ck t is address and control input setup time 0.9 ? 0.9 ? ns t ds dq and dm setup time to dqs 0.5 ? 0.5 ? ns t dh dq and dm hold time to dqs 0.7 ? 0.7 ? ns t hp clock half period t ch or t cl ?t ch or t cl ?ns t qh output dqs valid window t hp - 0.5 ? t hp - 0.55 ? ns t rc row cycle time 12 ? 11 ? t ck t rfc refresh row cycle time 14 ? 12 ? t ck t ras row active time 8 100k 7 120k t ck t rcdrd ras to cas delay in read 4 ? 4 ? t ck t rcdwr ras to cas delay in write 2 ? 2 ? t ck t rp row pre-charge time 3 ? 3 ? t ck t rrd row active to row active delay 2 ? 2 ? t ck t wr write recovery time 2 ? 2 ? t ck t cdlr last data-in to read command 2 ? 2 ? t ck t ccd column address to column address delay 1 ? 1 ? t ck t mrd mode register load delay 2 ? 2 ? t ck t dal auto pre-charge write recovery + pre-charge 7 ? 7 ? t ck t xsa self refresh exit to read command delay 200 ? 200 ? t ck t pdex power down exit time t is + 2 x t ck ?t is + 2 x t ck ?ns t ref refresh interval time ? 7.8 ? 7.8 s notes: 1. operating outside the ?absolute maximum ratings? may lead to temporary or permanent device failure. 2. power up sequence describe in ?initialization? section. 3. all voltages are referenced to vss.
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a ac test conditions output load output z = 25 30 pf 25 v ref = 0.5 x v ddq v tt = 0.5 x v ddq ac test conditions parameter unit input signal levels v ref + 0.4v / v ref - 0.4v input signal slew rate 1v / ns input timing reference level v ref output timing measurement reference level v tt clk and clk signal maximum peak swing 1.5v reference level of input/ouput signals 0.5 x v ddq
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. 00d 02/15/06 issi ? is43r32400a functional description the 128mbit ddr sdram is a high-speed cmos device with four banks that operate at 2.5v. each 32mbit bank is organized as 4,096 rows of 256 columns for the x32 options. pre-fetch architecture allows read and write accesses to be double-data rate and burst oriented. accesses start at a selected column location and continue every half-clock cycle for a programmed number of times. the read or write operation begins with an active command to transmit the selected bank and row (a0-a11 bits are sampled). this is followed by a read or write command to sample the address bits again to determine the first column to access. when access to the memory is not necessary, the device can be put into a power down mode in which current con- sumption is minimized. prior to normal operation, the device must be initialized in a defined procedure to function properly. the following sections describe the steps of initialization, the mode register defini- tions, command descriptions, and device operation. initialization the ddr sdram must be powered-on and initial- ized in a series of defined steps for proper operation. first, power is applied simultaneously to vdd and vddq. after these reaching stable values, a vref is ramped up. if this sequence is not followed, latch- up could occur and cause damage to the device. the input cke must be asserted and held to a lvcmos low level during this time to prevent unwanted commands from being executed. the outputs i/o and dqs remain in high impedance until driven during a normal operation. once vdd, vddq, vref, and cke are stable values, the clock inputs can begin to be applied. for a time period of at least 200s, valid clk and clk cycles must be applied prior to any command being issued to the device. cke needs to then be raised to sstl 2 logic high and issue a nop or deselect command to initialize the internal logic of the dram. next, a pre-charge all command is given to the device, followed by a nop/deselect command on each clock cycle for at least trp. the load extended mode register should be issued to enable dll, followed by another series of nop/deselect commands for at least tmrd. after this time, the load mode register command should be issued to reset the dll, again followed by a series of nop or deselect commands for at least tmrd. (note: whenever the dll is reset, 200 clock cycles must occur prior to any read command.) the pre-charge command is then issued, with nop/ deselect commands for at least trp. next, two auto- refresh commands are issued, each followed by nop/deselect commands for at least trfc. at this point, the jedec specification recommends that a ddr sdram receive another load mode register command to clear the dll, with nop/deselect commands for at least tmrd. the device is now ready to receive a valid command for normal opera- tion.
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a mode register definition the mode register allows configuration of the operat- ing mode of the ddr sdram. this register is loaded as a step in the normal initialization of the device. the load mode register command samples the values on inputs a0-a11, ba0 (low) and ba1 (low) and stores them as register values m0-m13. the values in the register determine the burst length, burst type, cas latency timing, and dll reset/clear. it should be noted that some bit values are reserved and should not be loaded into the register. the data in the mode register is retained until it is re-loaded or the ddr sdram loses its power (except for bit m8, which is cleared automatically). the register can be loaded only if all banks are idle. after the load mode register command, a minimum time of tmrd must pass before the subsequent command is issued. cas latency after a read command is issued to the device, a latency of several clock cycles is necessary prior to the validity of data on the data bus. also known as cas latency (cl), the value can be configured as 3, 4, or 5 depending on the bits m4-m6 loaded into the register. some cl values are not defined for certain speed ratings, and if they are used, the device may not function properly. mode register definition latency mode m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 reserved 1 1 1 reserved operating mode m8 m7 m6-m0 mode 0 0 defined standard operation 1 0 defined standard operation w/dll reset ? ? ? all other states reserved burst type m3 type 0 sequential 1 interleaved burst length m2 m1 m0 m3=0 m3=1 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved address bus (ax) mode register (mx) ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operating mode m13 m12 m11 m10 m9 mode 0 0 0 0 0 standard operation ? ? ? ? ? all other states reserved
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. 00d 02/15/06 issi ? is43r32400a burst definition burst starting column order of accesses in a burst length address sequential interleaved a2 a1 a0 2 0 0-1 0-1 1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full starting cn, cn + 1, cn + 2 not supported page address 0 ?cn - 1, (up to 256) n = a0-a7 cn? burst length the highest access throughput of this device can be achieved by using a burst of either read or write accesses. the number of accesses in each burst would be pre-configured to be 2, 4, 8, or full page as shown in mode register definition (bits m0-m2). when a read or write command is given to the device, the address bits a0-a7 (x32) select the block of columns and the starting column for the subsequent burst. the accesses in this burst can only reference the selected block, and may wrap-around if a bound- ary is reached. the burst definition table indicates the relationship between the least significant address bits and the starting column. the most significant address bits can select any unique block of columns in the currently activated row. (note: full page bursts are possible only in sequential mode, with the starting address even.) burst type bursts can be made in either of two types: sequential or interleaved. the burst type is programmed during a load mode register command (bit m3). during a read or write burst, the order of accesses is deter- mined by burst length, starting column, and burst type, as indicated in the burst definition table. dll reset/clear to cause a dll reset, the bit m8 is set to 1 in the load mode register command. when the dll is reset, 200 clock cycles are required to occur prior to any read operation. to clear the dll for normal operation, the bit m8 is set to 0. this device does not require it, but jedec specifications require that any time that the dll is reset, it later be cleared prior for normal operation.
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a extended mode register definition drive strength e6 e5 e4 e3 e2 e1 type 000000 full strength 000001 weak-60% 100001 matched impedence ?????? all o ther states reserved operating mode e13 e12 e11 e10 e9 e8 e7 mode 0100000 standard operation ???????all other sta tes reserved dll e0 status 0 enable 1 disable ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus (ax) mode register (ex) extended mode register definition the extended mode register is a second register to enable additional functions of the ddr sdram. this register is loaded as a step in the normal initialization of the device. the load extended mode register command samples the values on inputs a0-a11, ba0 (high) and ba1 (low) and stores them as register values e0-e13. the additional functions are dll enable/disable and output drive strength. similarly to the load mode register, the load extended mode register has reserved bit values, a bank idle pre- requisite, and a tmrd time requirement. the data in the mode register is retained until it is reloaded or the device loses its power. dll enable/disable when the load extended mode register command is issued, dll should be enabled (e0 = 0). normal operation of the device requires this, but dll can be disabled for debugging or evaluation, if necessary. output drive strength normal drive strength for the outputs is specified as sstl 2. however, there are options for reduced drive strength included.
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. 00d 02/15/06 issi ? is43r32400a commands all commands described in this section should be issued only when the initialization sequence is obeyed. deselect this feature blocks unwanted commands from being executed. chip select ( cs ) must be taken high to cause deselect. operations that are underway are not affected. no operation (nop) nop is a command that prevents new commands from being executed. cs must be low, while ras , cas , and we must be high to issue nop. nop or deselect commands must be issued during wait states to allow operations that are underway to continue uninter- rupted. load mode register the base mode register is loaded during a step of initialization to configure the ddr sdram. load mode register (lmr) is issued when ba0 and ba1 are low, and a0-a11 are selected according to the mode register definition. load extended mode register the extended mode register is loaded during a step of initialization to enable the dll of the device. load extended mode register (lmr) is issued when ba0 is high, ba1 is low, and a0-a11 are selected according to the extended mode register definition. read the read command is used to begin a burst read access. when the command is given to the device, the ba0 and ba1 inputs select the bank, and address bits a0-a7 (x32) select the block of columns and the starting column for the subsequent burst. the cross- ing of the clk and clk signals will cause the output values on the i/o pins to be valid. the auto pre- charge function is one option in the read command. if the auto pre-charge is enabled, the currently selected row will be pre-charged following the read burst. if the function is not enabled, the selected row will remain open for further accesses at the end of the read burst. write the write command is used to begin a burst write access. when the command is given to the device, the ba0 and ba1 inputs select the bank, and address bits a0-a7 (x32) select the block of columns and the starting column for the subsequent burst. the rising edge on the data strobe input(s) will cause the input values on the data mask pin(s) and i/o pins to be sampled for the write operation. the auto pre-charge function is one option in the write command. if the auto pre-charge is enabled, the currently selected row will be pre-charged following the write burst. if the function is not enabled, the selected row will remain open for further accesses at the end of the write burst. pre-charge a pre-charge command will de-activate an open row in a bank. the input a8 (x32) is sampled at this time to determine whether pre-charge is applied to a single bank or all banks. after trp, the bank has been pre- charged. it is de-activated, and goes into the idle state and must be activated before any read or write command can be issued to it. a pre-charge command is treated as a nop if either (a) the specified bank is already undergoing pre-charge, or (b) the specified bank has no open row. auto pre-charge auto pre-charge is a feature that can be enabled as an option in a read or write command. if the input value on a8 (x32) is high during a read or write command, an automatic pre-charge will occur just after the memory burst is completed. if the input value on a8 (x32) is low, no pre-charge will occur. with auto pre-charge, a minimum time of trp must pass before the next command is issued to the same bank. active the active command opens a row in preparation for a read or write burst. the row stays open for accesses until the bank receives a pre-charge command. other rows in the bank cannot be opened until the bank is de-activated with a pre-charge command and another active command is issued. burst terminate the burst terminate command truncates the burst of the most recently issued read command (with auto pre-charge disabled). the open row being accessed in the read burst remains open.
18 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a auto refresh the ddr sdram is issued the auto refresh com- mand during normal operation to maintain data in the memory array. all the banks must be idle for the command to be executed. the device has 4096 refresh cycles every 32ms. self refresh to issue the self refresh command, cke must be low. when the ddr sdram is in self refresh mode, it retains the data contents without external clocking, and ignores other input signals. the dll is disabled upon entering the self refresh mode, and is enabled again upon leaving the mode. to exit self refresh, all inputs must be stable prior to cke going high. next, a nop command command must be issued on each clock cycle for at least txsnr to ensure that internal refresh operations are completed. to prepare for a memory access, the ddr sdram must receive a dll reset followed by a nop command for 200 clock cycles. device operation bank and row activation an active command must be issued to the ddr sdram to open a bank and row prior to an access. the row will be available for a read or write com- mand once a time trcd has occurred. the active command is depicted in the figure. as clk goes high, cs and ras are low, while cke, we , and cas are high. upon issuing the active command, the values on the address inputs specify the row, and ba0 and ba1 specify the bank. when an active command is issued for a bank and row, another row in that same bank may be activated after a time trc. when an active command is issued for a bank and row, a row in a different bank may be activated after a time trrd. (note: to ensure that time requirement trcd, trc, or trrd is met, nop commands should be issued for a whole number of clock cycles that is greater than the time requirement (ie. trcd) divided by the clock period.) read operation a read command starts a burst from an activated row. the read command is depicted in the figure. as clk goes high, cs and cas are low, while ras , cke, and we are high. the values on the inputs ba0 and ba1 specify the bank to access, and the address inputs specify the starting column in the open row. if auto pre-charge is enabled in the read command, the open row will be pre-charged after completion of the read burst. unless stated otherwise, all timing dia- grams for read operations have disabled auto pre- charge. the read command causes data to be retrieved and placed in the pipeline. the subsequent command can be nop, read, or terminate burst. the data from the starting column specified in the read command appears on i/o pins following a cas latency of after the read command. on each clk and clk crossing, the data from the next column in the burst sequence is output from the pipeline until the burst is completed (see read burst, non-consecutive read burst, and consecutive read burst). there are two cases in which a full read burst length is not completed. the first is when the data retrieved from a subsequent read burst interrupts the previous burst (see random read accesses). the second is when a subsequent burst terminate command truncates the burst (see terminating a read burst and read to write). the burst terminate and read commands obey the same cas latency timing such that they should be issued x cycles after a previous read command, where x is the number of pairs of columns to output. by following a desired command sequence, continuous data can be output with either whole read bursts or truncated read bursts. whenever a read burst finishes and no other commands have been initiated, the i/o returns to high-z. if auto pre-charge is not enabled in the read burst, the pre-charge command can be issued separately following the read command. the pre-charge com- mand should be received by the device x cycles after the read command, where x is the desired number of pairs of columns to output during the read burst. after the pre-charge command, it is necessary to wait until both tras and trp have been met before issuing a new command to the same bank. data strobe output is driven synchronously with the output data on the i/o pins. the low portion of the data strobe just prior to the first output data is the read pre-amble; and the low portion coinciding with the last output data is the read post-amble. before any write command can be executed, any previous read burst must have been completed normally or truncated by a burst terminate command. in the diagram read to write, a burst terminate command is issued to truncate a read burst early, and begin a write operation. after the write command, a time tdqss is required prior to latching the data on the i/o.
integrated silicon solution, inc. ? 1-800-379-4774 19 rev. 00d 02/15/06 issi ? is43r32400a write operation a write command starts a burst from an activated row. the write command is depicted in the figure. as clk goes high, cs , we , and cas are low, while cke and ras are high. the values on the inputs ba0 and ba1 specify the bank to access, and the address inputs specify the starting column in the open row. if auto pre-charge is enabled in the write command, the open row will be pre-charged after completion of the write burst and time twr. unless stated otherwise, all timing diagrams for write operations have disabled auto pre-charge. the write command in conjunction with data strobe inputs causes data to be latched and placed in the pipeline. the low portion of the data strobe between the write command and the first rising edge of the strobe is the write pre-amble; and the low portion following the last input data is the write post-amble. a minimum time of tdqss after the write, the next command can be nop or write. the data that is to be written to the starting column specified in the write command will be latched upon the first rising edge of data strobe input(s) dqs0-dqs3 (x32) after that write command. on each data strobe transition from low-to-high or high-to-low, the input values on the i/ o are sampled, and enter pipeline to be written in the pre-determined burst sequence (see write burst, consecutive write to write, and non-consecutive write to write). a new write command can be issued x cycles after a previous write command, where x is the number of pairs of columns to input. by following a desired command sequence, continuous data can be input with either whole write bursts or truncated write bursts. whenever a write burst finishes and no other commands have been initiated, the i/o returns to high-z. a write burst may be followed by read command, with or without truncating the write burst. to avoid truncat- ing the input data, the timing parameter twtr should be obeyed before issuing the read command (see write to read, non-truncated). the period twtr begins on the first positive clock edge after the last data input has been latched. the write burst can be truncated deliberately by using the data mask feature and a read command with an earlier timing (see write to read, truncated). if auto pre-charge is not enabled in the write burst, the pre-charge command can be issued separately some time following the write command. the proce- dure to execute it is similar to the procedure to transi- tion from a write burst to a read burst. to avoid truncating the input data, the timing parameter twr should be obeyed before issuing the pre-charge command (see write to pre-charge, non-truncated). the period twr begins on the first positive clock edge after the last data input has been latched. the write burst can be truncated deliberately by using the data mask feature and a pre-charge command with an earlier timing (see write to pre-charge, truncated). after the pre-charge command, it is necessary to wait until trp has been met before issuing a new command to the same bank. power down operation when the ddr sdram enters power down mode, power consumption is greatly reduced. to enter the mode, several conditions must be met. there must be neither a read operation, nor a write operation underway in the device at clk positive edge n ? 1, with cke stable high. prior to clk positive edge n, cke should go low. a power down mode is entered if the appropriate command is issued as clk n goes high. (if the command at clk n is auto refresh, the sdram enters self refresh mode.) if the command at clk n is nop or deselect, the device will enter pre- charge power down mode or active power down mode. while in a power down mode, cke must be stable low, and clk and clk signals maintained, while other inputs are ignored. pre-charge power down mode conserves additional power by freezing the dll. to exit the power down mode, normal voltages and clock frequency are applied. prior to clk positive edge n, cke should go high. a nop or deselect command at clk n, allows a valid command to be issued at clk positive edge n + 1. (if exiting self refresh mode, the dll is automatically enabled, and the device must be prepared according to the section describing self refresh.) pre-charge operation when this command is issued, either a particular bank, or all four banks will be de-activated after a time period of trp. the bank(s) will be available for a row access until that time has occurred. the pre-charge command is depicted in the figure. as clk goes high, cs , ras , and we are low, while cke and cas are high. the values on the address inputs are don?t care, except for the input a8 (x32), which determines whether a single bank is selected for pre-charge, or all four banks. if a8 is low, the inputs ba0 and ba1 select the single bank; however, if a8 is high, ba0 and ba1 are don?t care. once any bank has been pre-charged, it becomes idle. before any row can have a read or write access, it must be activated.
20 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a timing waveforms figure 1. ac parameters for read timing ( burst length =4) figure 2. ac parameters for write timing (burst length=4 ) cmd ck# ck a0-11, dqs dm dq
integrated silicon solution, inc. ? 1-800-379-4774 21 rev. 00d 02/15/06 issi ? is43r32400a
22 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a figure 6. write with auto precharge (burst length = 4) figure 7. read burst interrupt by read (cas letancy =5, burst length = 4 ) figure 8. write interrupted by write (burst length =4) figure 9. auto refresh timing
integrated silicon solution, inc. ? 1-800-379-4774 23 rev. 00d 02/15/06 issi ? is43r32400a figure 11. precharge command t mrd
24 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00d 02/15/06 issi ? is43r32400a ordering information commercial range: 0c to +70c frequency speed (ns) order part no. package 200 mhz 5 IS43R32400A-5B 144-ball fbga 200 mhz 5 IS43R32400A-5Bl 144-ball fbga, lead-free 166 mhz 6 is43r32400a-6b 144-ball fbga 166 mhz 6 is43r32400a-6bl 144-ball fbga, lead-free industrial range: -40c to +85c frequency speed (ns) order part no. package 166 mhz 6 is43r32400a-6bi 144-ball fbga 166 mhz 6 is43r32400a-6bli 144-ball fbga, lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 05/23/05 copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (144-ball) mbga - 12mm x 12mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 144 a 1.17 1.25 1.40 0.046 0.049 0.055 a1 0.32 0.35 0.38 0.013 0.014 0.015 d 11.95 12.00 12.05 0.470 0.472 0.474 d1 ? 8.80 ? ? 0.346 ? e 11.95 12.00 12.05 0.470 0.472 0.474 e1 ? 8.80 ? ? 0.346 ? e ? 0.80 ? ? 0.031 ? notes: 1. controlling dimensions are in millimeters. 2. 0.8 mm ball pitch 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a b c d e f g h j k l m ? 0.45 + /? 0.05 (144x) d e e a1 seating plane a d1 e1 e 12 11 10 9 8 7 6 5 4 3 2 1

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